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JLC1562B I2C Bus I/O Expander
The JLC1562B facilitates easy I2C Bus expandibility. Multiple devices (up to 8 on the same I2C Bus) are easily added as each device has its own selectable 3-bit address. The JLC1562B provides an 8-bit bidirectional input/output port and 6-bit resolution Digital to Analog Converter. The device can also be used as an Analog to Digital Converter with 5 input signal lines each with 6-bit A/D resolution. The voltage on pins P0-P4 is compared with a controllable threshold voltage and the results are readable through the I2C Bus. I2C Bus interface pins SDA, SCL and A0-A2 are; Serial Data, Serial Clock and Device Address respectively. External interface pins are P0-P7 and VDAC; I/O Port and D/A output.
Features
http://onsemi.com MARKING DIAGRAMS
16 PDIP-16 N SUFFIX CASE 648 1 16 EIAJ-16 F SUFFIX CASE 966 1 A = Assembly Location WL or L = Wafer Lot YY or Y = Year WW or W = Work Week JLC1562B ALYW JLC1562BN AWLYYWW
* * * * * * * *
Low Power Dissipation I2C-Bus Format (2-wire type; SDA, SCL) Data Transfer 6-bit A/D Converter Bus Address Selectable (3-bit) Address Input pins are pulled up to Vdd with internal resistor I/O pins are Open Drain Outputs Analog Input through Comparator Inputs Protected from External Bus Currents in Power Down mode
PIN ASSIGNMENT
A0 Power-On Reset A1 A2 P0 P7 P6 P5 P4 P3 P2 P1 P0 VDAC P1 P2 P3 VSS 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 VDD SDA SCL VDAC P7 P6 P5 P4
SDA 8 Bit I2C Bus Controller 6 Bit Latch 6-Bit DAC Latch SCL VDD Write Buffer
Shift Register (PISO) (SIPO)
PIN LIST
A0-A2 P0-P4 P5-P7 SCL SDA Chip Address Input Comparator Input / Open Drain Output Comparator Input / Open Drain Output Serial Clock Input I2C Data Output DAC Output
A0 A1 A2
1/2 VCC Comp. A (C5-C7) Latch 5 Bit 5 Bit 3 Bit
VDAC
Comp. B (C0-C4)
ORDERING INFORMATION
Device JLC1562BN JLC1562BF JLC1562BFEL Package PDIP-16 EIAJ-16 EIAJ-16 Shipping 500 / Unit Pak 50 Units / Rail 2000 Units / Reel
NOTE: Internal Power On Reset sets P0 P7 low, sets VDAC to 1/80 VDD and selects 1/2 VDD for Comparator "B" threshold.
Figure 1. Block Diagram
(c) Semiconductor Components Industries, LLC, 1999
1
March, 2000 - Rev. 1
Publication Order Number: JLC1562BE/D
JLC1562B
VDD 16 X R65 Comparator "B" Vref Pin 1 VDAC
R64
R63 Write Data (2) Vref Selector Bit D6 of Write Data (2) R40 R39 D6 1 0 Vref Value Vref = VDAC V ref
+ 40 80
V
DD
Write Data (2) R2 R1 GND D5 1 D4 1 D3 1 D2 1 * * * * 1 + 80 0 V DD 0 0 0 0 0 0 0 0 0 1 0 D1 1 D0 1 Vref 64 V 80 DD * * * * 2V 80 DD 1V 80 DD
6:64 De-Mux (1 of 64 Decoder) Bits D0 - D5 of Write Data (2)
1LSB
III I I I I IIIIIIIIIIIIIIIIIIIIIII II I I III I I I I IIIIIIIIIIIIIIIIIIIIIII II I I IIIIIIIIIIIIIIIIIIIIIII II I I IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIIIII II I II I IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII II I III II I IIIIIIIIIIIIIIIIIIIIIII II I III II I IIIIIIIIIIIIIIIIIIIIIII II I IIIIIIIIIIIIIIIIIIIIIII II I IIIIIIIIIIIIIIIIIIIIIII II I IIIIIIIIIIIIIIIIIIIIIII II I IIIIIIIIIIIIIIIIIIIIIII II I IIIIIIIIIIIIIIIIIIIIIII II I IIIIIIIIIIIIIIIIIIIIIII II I IIIIIIIIIIIIIIIIIIIIIII II I IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIIIII II I I IIIIIIIIIIIIIIIIIIIIIII II I IIIIIIIIIIIIIIIIIIIIIII II I IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIIIIIIIIII
MAXIMUM RATINGS (Referenced to GND)
Symbol Vdd Vin Parameter Value Unit V V V DC Supply Voltage DC Input Voltage - 0.5 to + 7.0 - 0.5 to Vdd + 0.5 - 0.5 to Vdd + 0.5 25 75 Vout I DC Output Voltage DC Input/Output Current (per Pin) mA mA IDD DC Supply Current (VDD and GND Pins) Storage Temperature Range Tstg TL - 65 to + 150 300
_C _C
Lead Temperature, 1 mm from Case for 10 Seconds
RECOMMENDED OPERATING CONDITIONS
Symbol Vdd Parameter
Min 4.2 0.0
Max 6.0
Unit V V
DC Supply Voltage DC Input Voltage
Vin, Vout TA
Vdd
Operating Temperature
- 40
+ 85
_C
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JLC1562B
DC CHARACTERISTICS (Referenced to Vss)
Guaranteed Limit Symbol VIH VIL VOL Iin Ioz Cin Cout Ci/o VICR ICC Maximum Input Voltage, "H" Maximum Input Voltage, "L" Maximum Output Voltage, "L" (Iout = 4mA) Maximum Input Leakage Current (Vin = Vdd or Vss, SCL pin only) Maximum Output Hi-Z Leakage Current (Output = High Impedance; Vout = Vdd) Maximum Input Capacitance (Input Pin) Maximum Output Capacitance (Output Pin) Maximum I/O Capacitance (I/O Pin) Comparator Common Mode Input Voltage Range Maximum Quiescent Supply Current (per Package) Parameter Min 0.7 Vdd - - - - - - - 0 - Max - 0.3 Vdd 0.3 1.0 5.0 10 15 15 Vdd - 1.5 5.0 Unit V V V A A pF pF pF V mA
COMPARATOR AC CHARACTERISTICS
Guaranteed Limit Symbol tPD Parameter Maximum Propagation Delay Test Conditions Vref = 1.5V, 10mV overdrive Vref = 1.5V, 100mV overdrive Min - - Typ 1.0 0.2 Max - - Unit S S
DA COMPARATOR CHARACTERISTICS
Guaranteed Limit Symbol DNL eFS eZC Parameter DAC Referential NON-Linearity DAC Full Scale Error DAC Zero Scale Error Min Typ 1/4 LSB 1 LSB 1 LSB Max Unit
TIMING CHARACTERISTICS
Guaranteed Limit Symbol fCL tBUF tHD:STA tLOW tHIGH tHD:DAT tSU:DAT tR tF tSU:STO SCL CLOCK Frequency BUS Free Time (Between "STOP" and "START") HOLD Time for "START" HOLD Time at SCL CLOCK LOW HOLD Time at SCL CLOCK HI DATA HOLD Time DATA SETUP Time Rise Time (SDA and SCL) Fall Time (SDA and SCL) SETUP Time for "STOP" Parameter Min 0 4.7 4.0 4.7 4.0 0 250 - - 4.0 Max 100 - - - - - - 1000 300 - Unit kHz s s s s s ns ns ns s
SDA tBUF SCL tLOW tR tF
tHD:STA
tHD:DAT
tHIGH
tSU:DAT
tSU:STO
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JLC1562B
READ / WRITE MODES SDA MODE Master Device READ WRITE Receiver Transmitter Slave Device Transmitter Receiver I/O Port Input Output SDA SCL I/O Expander
Micro Controller (Master Device)
I/O Expander (Slave Device)
SDA SCL P0 - P7
The JLC1562B Supports the following types of Bus Cycles 1.) WRITE MODE (A)
S Slave Address & R/W SACK Write Data (1) SACK P
2.) WRITE MODE (B)
S Slave Address & R/W SACK Write Data (1) SACK Write Data (2) SACK P
3.) READ MODE (A)
S Slave Address & R/W SACK Read Data MACK P
4.) READ MODE (B)
S Slave Address & R/W SACK Read Data (1) MACK Read Data (2) MACK Read Data (3) MACK P
S = START Condition SACK = Slave Acknowledgement MACK = Master Acknowledgement P = STOP Condition
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JLC1562B
READ WRITE DATA FORMAT <>
S 0 1 1 1 A2 A1 A0 1 ACK D7 D6 D5 D4 D3 D2 D1 D0 ACK P
Slave Address
Read Data
Slave Address
A0 - A2
I/O Expander Device Address (Pins A0 - A2)
A3 - A6
A6
A5
A4
A3
is hard wired as
0
1
1
1
R/W
1 : READ ADDRESS
Read Data
D5 - D7
Output of Comparator "A". (Vth = 1/2 VDD)
D0 - D4
Output of Comparator "B". (Vth = 1/2 VDD OR VDAC) READ LATCH Bit Controls when Data Will Be Latched.
<>
S 0 1 1 1 A2 A1 A0 0 ACK D7 D6 D5 D4 D3 D2 D1 D0 ACK D7 D6 D5 D4 D3 D2 D1 D0 ACK P
Slave Address
Write Data (1)
Write Data (2)
Slave Address
A0 - A2 A3 - A6 R/W
I/O Expander Device Address (Pins A0 - A2)
A6 A5 A4 A3
is hard wired as
0
1
1
1
0 : WRITE ADDRESS
Write Data (1)
D0 - D7
Device Pins P0 to P7 Output Bits.
Write Data (2)
D7
READ LATCH CONTROL
Latch Control of Signals C0 - C4 in the Device BLOCK DIAGRAM
0 : Data is latched at the ACK after a READ COMMAND. 1 : Data is latched when Comparator "B" switches from 0 to 1. (switch point is controlled by Vth.) 1 : Data is reset at the ACK after a READ COMMAND. D6 COMPARATOR "B" Vref Control Bit 0:V ref
+ 40 VDD 80 1:V +V ref DAC
D0 - D5
DAC Input Bits
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JLC1562B
<> 1234567891234 SCL WRITE COMMAND DATA (I) DATA (II) 56789123456789
SDA Write_buffer Latch Pulse I/O Port (P0 - P7) DAC Latch Pulse DAC Latch
S0
111xxx0A
A
AP
DATA (I) valid
DATA (II) valid
<> (READ LATCH = 0) 1234567891234 SCL READ COMMAND DATA (I) + (II) 56789
SDA PISO Load Pulse Comp_out (C0 - C4) Comp_out (C5 - C7)
S0 111 xx x 1A
AP
DATA (I)
DATA (II)
<> (READ LATCH = 1) 123456789 SCL WRITE DATA (II) READ COMMAND DATA (I) 1234 56789123456789
SDA
1
AP
S0
111xxx1A
AP
DAC Latch D7 (READ LATCH Bit) LATCH Reset
Comp._out
Latched Data PISO Load Pulse
DATA (I)
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JLC1562B
PACKAGE DIMENSIONS
-A -
16 9
B
1 8
PDIP-16 N SUFFIX CASE 648-08 ISSUE R
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. 5. ROUNDED CORNERS OPTIONAL. DIM A B C D F G H J K L M S INCHES MILLIMETERS MIN MAX MIN MAX 0.740 0.770 18.80 19.55 0.250 0.270 6.35 6.85 0.145 0.175 3.69 4.44 0.015 0.021 0.39 0.53 0.040 0.070 1.02 1.77 0.100 BSC 2.54 BSC 0.050 BSC 1.27 BSC 0.008 0.015 0.21 0.38 0.110 0.130 2.80 3.30 0.295 0.305 7.50 7.74 0 10 0 10 0.020 0.040 0.51 1.01
F S
C
L
-T - H G D 16 PL 0.25 (0.010)
M
SEATING PLANE
K
J TA
M
M
F SUFFIX CASE 966-01 ISSUE O
16
9
LE Q1 E HE M_ L DETAIL P
1
8
Z D e A VIEW P
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS D AND E DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS AND ARE MEASURED AT THE PARTING LINE. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 5. THE LEAD WIDTH DIMENSION (b) DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE LEAD WIDTH DIMENSION AT MAXIMUM MATERIAL CONDITION. DAMBAR CANNOT BE LOCATED ON THE LOWER RADIUS OR THE FOOT. MINIMUM SPACE BETWEEN PROTRUSIONS AND ADJACENT LEAD TO BE 0.46 ( 0.018). DIM A A1 b c D E e HE L LE M Q1 Z MILLIMETERS MIN MAX --- 2.05 0.05 0.20 0.35 0.50 0.18 0.27 9.90 10.50 5.10 5.45 1.27 BSC 7.40 8.20 0.50 0.85 1.10 1.50 10 _ 0_ 0.70 0.90 --- 0.78 INCHES MIN MAX --- 0.081 0.002 0.008 0.014 0.020 0.007 0.011 0.390 0.413 0.201 0.215 0.050 BSC 0.291 0.323 0.020 0.033 0.043 0.059 10 _ 0_ 0.028 0.035 --- 0.031
c
b 0.13 (0.005)
M
A1 0.10 (0.004)
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JLC1562B
NOTE: The "E" in this Publication Order Number denotes English version. The Japanese version of this document is available from Japan as JLC1562B/D
ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer.
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JLC1562BE/D

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